Table 6-1 summarizes the available family members.
Table 6-1 Device Comparison
| DEVICE(1)(2) |
FRAM (KB) |
SRAM (KB) |
CLOCK SYSTEM |
LEA |
USS USSXT |
MTIF |
ADC12_B (Channels) |
Comp_E (Channels) |
Timer_A(3) |
Timer_B(4) |
eUSCI_A(5) |
eUSCI_B(6) |
AES |
BSL |
I/Os |
PACKAGE |
| MSP430FR6047 |
256 |
8 |
DCO
HFXT
LFXT |
Yes |
Yes |
Yes |
16 external, 2 internal |
16 |
3, 3(7)
2, 2,2(8) |
7 |
4 |
2 |
Yes |
UART |
76 |
100 PZ (LQFP) |
| MSP430FR60471 |
256 |
8 |
DCO
HFXT
LFXT |
Yes |
Yes |
Yes |
16 external, 2 internal |
16 |
3, 3(7)
2, 2,2(8) |
7 |
4 |
2 |
Yes |
I2C |
76 |
100 PZ (LQFP) |
| MSP430FR6037 |
256 |
8 |
DCO
HFXT
LFXT |
Yes |
No |
Yes |
16 external, 2 internal |
16 |
3, 3(7)
2, 2,2(8) |
7 |
4 |
2 |
Yes |
UART |
76 |
100 PZ (LQFP) |
| MSP430FR60371 |
256 |
8 |
DCO
HFXT
LFXT |
Yes |
No |
Yes |
16 external, 2 internal |
16 |
3, 3(7)
2, 2,2(8) |
7 |
4 |
2 |
Yes |
I2C |
76 |
100 PZ (LQFP) |
| MSP430FR6045 |
128 |
8 |
DCO
HFXT
LFXT |
Yes |
Yes |
Yes |
16 external, 2 internal |
16 |
3, 3(7)
2, 2,2(8) |
7 |
4 |
2 |
Yes |
UART |
76 |
100 PZ (LQFP) |
| MSP430FR6035 |
128 |
8 |
DCO
HFXT
LFXT |
Yes |
No |
Yes |
16 external, 2 internal |
16 |
3, 3(7)
2, 2,2(8) |
7 |
4 |
2 |
Yes |
UART |
76 |
100 PZ (LQFP) |
(1) For the most current package and ordering information, see the
Package Option Addendum in
Section 12, or see the TI website at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I2C with multiple slave addresses and SPI.
(7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any) whereas Timer TA4 provides internal, external capture/compare inputs and internal, external PWM outputs.