Six input channels connected to external
single-ended signals that are source applied to
subminiature version A (SMA) connectors or
headers.
Serial and parallel interface connects to the PHI
controller via a 60-pin connector (J2).
High-voltage power supplies (HVDD and HVSS) are
not included. Connect common lab supplies via screw terminal J1.
Analog low-voltage supplies (AVDD = 5 V) are
generated using an external 15-V supply and a
low-dropout regulator (LDO). HVDD (12-V supply) is
also generated using the 15-V supply and an LDO.
HVSS (–12-V supply) is generated using the –15-V
supply and an LDO.
Digital low-voltage supply (DVDD = 3.3 V) is
generated using USB power from the PHI
controller.
Integrated or external voltage reference options
are available.