SLAU298A November 2009 – May 2021
- Trademarks
- 1ADS8555EVM-PDK Overview
- 2EVM Analog Interface
- 3Digital Interface
- 4Power Supplies
- 5Installing the ADS8555EVM Software
-
6ADS8555EVM Operation
- 6.1 Connecting the Hardware and Running the GUI
- 6.2 Jumper Settings for the ADS8555EVM
- 6.3 Modifying Hardware and Using Software to Evaluate Other Devices in the Family
- 6.4 EVM GUI Global Settings for ADC Control and Registers
- 6.5 Time Domain Display
- 6.6 Frequency Domain Display
- 6.7 Histogram Display
- 7Bill of Materials, Layout, and Schematics
- 8Revision History
4.3 Low-Dropout Regulator (TPS7A4700 for AVDD, HVDD)
The 15-V external power is connected to two LDOs (TPS7A4700RGWR). One LDO generates AVDD (5 V), and one generates HVDD (12 V). As shown in Figure 4-3, the TPS7A4700RGWR LDO output can be programmed to different voltages by installing or uninstalling the resistors connected on pins 4-12. This LDO was selected for low noise and flexibility.
Figure 4-3 Low-Dropout Regulator (TPS7A4700
for AVDD, HVDD)