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14.2.11.2.2 CBC Decryption
For CBC decryption, the first block of data needs some special handling because the output must be XORed with the Initialization Vector. For that purpose, the DMA triggered by 'AES trigger 0' must be configured to read the data from the Initialization Vector first and then must be reconfigured to read from the ciphertext.
Figure 14-9 CBC Decryption To implement the CBC decryption without CPU interaction, three DMA channels are needed. Static DMA priorities must be enabled. The DMA triggers must be configured as level-sensitive triggers.
Table 14-6 AES and DMA Configuration for CBC Decryption
| AES
CMEN |
AES
CMx |
AES
OPx |
DMA_A
Triggered by 'AES trigger 0' |
DMA_B
Triggered by 'AES trigger 1' |
DMA_C
Triggered by 'AES trigger 2' |
|---|---|---|---|---|---|
| 1 | 01 | 01 or 11 | Write the previous ciphertext block to AESAXIN | Read plaintext from AESADOUT | Write next plaintext to AESADIN, which also triggers the next decryption |
The following pseudo code snippet shows the implementation of the CBC decryption in software:
CBC_Decryption(key, IV, plaintext, ciphertext, num_blocks)
// Pseudo Code
{
Generate Decrypt Key:
Configure AES:
AESCMEN= 0; AESOPx= 10;
Write key into AESAKEY;
Wait until key generation completed;
Configure AES for block cipher:
AESCMEN= 1; AESCMx= CBC; AESOPx= 11;
AESKEYWR= 1; // Use previously generated key
Setup DMA:
DMA0: Triggered by AES trigger 0,
Source: IV, Destination: AESAXIN,
Size: 8 words, Single Transfer mode
DMA1: Triggered by AES trigger 1,
Source: AESADOUT, Destination: plaintext,
Size: num_blocks*8 words, Single Transfer mode
DMA2: Triggered by AES trigger 2,
Source: ciphertext, Destination: AESADIN,
Size: num_blocks*8 words, Single Transfer mode
Start decryption:
AESBLKCNT= num_blocks;
Wait until first block is decrypted: DMA0IFG=1;
Setup DMA0 for further blocks:
DMA0: // Write previous cipher text into AES module
Triggered by AES trigger 0,
Source: ciphertext, Destination: AESAXIN,
Size: (num_blocks-1)*8 words, Single Transfer mode
End of decryption: DMA1IFG=1
}