SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The Extended Scan IF has one interrupt vector for nine interrupt flags listed in Table 37-7. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt. The interrupt flags are not automatically cleared. They must be cleared with software. The interrupt vector register ESIIV is used to determine which interrupt flags requested an interrupt.
| Interrupt Flag | Interrupt Condition |
|---|---|
| ESIIFG0 | ESIIFG0 is set by one of the ESIOUT0 to ESIOUT3 outputs selected with the ESIIFGSET1x bits. |
| ESIIFG1 | ESIIFG1 is set by the rising edge of the ESISTOP(tsm) signal. |
| ESIIFG2 | ESIIFG2 is set at the start of a TSM sequence. |
| ESIIFG3 | ESIIFG3 is set at different count intervals of the ESICNT1 counter, selected with the ESITHR1 and ESITHR2 registers. |
| ESIIFG4 | ESIIFG4 is set at different count intervals of the ESICNT2 counter, selected with the ESIIS2x bits. |
| ESIIFG5 | ESIIFG5 is set when the PSM transitions to a state with Q6 set. |
| ESIIFG6 | ESIIFG6 is set when the PSM transitions to a state with Q7 set. |
| ESIIFG7 | ESIIFG7 is set at different count intervals of the ESICNT0 counter, selected with the ESIIS0x bits. |
| ESIIFG8 | ESIIFG8 is set by one of the ESIOUT4 to ESIOUT7 outputs selected with the ESIIFGSET2x bits. |