SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Extended Scan Interface Analog Front-End Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | Reserved | Reserved | Reserved | ESIDAC2EN | ESICA2EN | ESICA2INV | ESICA1INV |
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESICA2X | ESICA1X | ESICISEL | ESICACI3 | ESISHTSM(1) | ESIVMIDEN(2) | ESISH | ESITEN |
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | Reserved | RW | 0h |
Reserved for test purposes. It is strongly recommended to always write these bits as 0. |
| 11 | ESIDAC2EN | RW | 0h |
Enable ESIDAC(tsm) control for DAC in AFE2. 0b = AFE2's DAC is always disabled, independently from ESIDAC(tsm) setting. 1b = AFE2's DAC is controlled by ESIDAC(tsm) bit. |
| 10 | ESICA2EN | RW | 0h |
Enable ESICA(tsm) control for comparator in AFE2. 0b = AFE2's comparator is always disabled, independently from ESICA(tsm) setting. 1b = AFE2's comparator is controlled by ESICA(tsm) bit. |
| 9 | ESICA2INV | RW | 0h |
Invert AFE2's comparator output 0b = Comparator output in AFE2 is not inverted 1b = Comparator output in AFE2 is inverted |
| 8 | ESICA1INV | RW | 0h |
Invert AFE1's comparator output 0b = Comparator output in AFE1 is not inverted 1b = Comparator output in AFE1 is inverted |
| 7 | ESICA2X | RW | 0h |
AFE2's comparator input select. This bit selects groups of signals for the comparator input. 0b = AFE2's comparator input is one of the ESICHx channels, selected with the channel select logic. 1b = AFE2's comparator input is one of the ESICIx channels, selected with the channel select logic and the ESICISEL and ESICACI3 bits. |
| 6 | ESICA1X | RW | 0h |
AFE1's comparator input select. This bit selects groups of signals for the comparator input. 0b = AFE1's comparator input is one of the ESICHx channels, selected with the channel select logic. 1b = AFE1's comparator input is one of the ESICIx channels, selected with the channel select logic and the ESICISEL and ESICACI3 bits. |
| 5 | ESICISEL | RW | 0h |
Comparator input select for AFE1 only. This bit is used with the ESICACI3 bit to select the comparator input when ESICAX = 1. 0b = Comparator input is one of the ESICIx channels, selected with the channel select logic and ESICACI3 bit. 1b = Comparator input is the ESICI channel |
| 4 | ESICACI3 | RW | 0h |
Comparator input select for AFE1 only. This bit is selects the comparator input when ESICISEL = 0 and ESICAX = 1. 0b = Comparator input is selected with the channel select logic. 1b = Comparator input is ESICI3. |
| 3 | ESISHTSM(1) | RW | 0h |
Sample-and-hold ESIDVSS select. 0b = The ground connection of the sample capacitor is connected to ESIDVSS, regardless of the TSM control. 1b = The ground connection of the sample capacitor is controlled by the TSM |
| 2 | ESIVMIDEN(2) | RW | 0h |
Mid-voltage generator 0b = AVCC/2 generator is off 1b = AVCC/2 generator is on if ESISH = 0 |
| 1 | ESISH | RW | 0h |
Sample-and-hold enable 0b = Sample-and-hold is disabled 1b = Sample-and-hold is enabled |
| 0 | ESITEN | RW | 0h |
Excitation enable 0b = Excitation circuitry is disabled 1b = Excitation circuitry is enabled |