SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Extended Scan Interface General Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ESIS3SELx | ESIS2SELx | ESIS1SELx | |||||
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESIS1SELx | ESITCH1x | ESITCH0x | ESICS | ESITESTD | ESIEN | ||
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | ESIS3SELx | RW | 0h |
PPUS3 source select. These bits select the PPUS3 source for the PSM. 000b = ESIOUT0 is the PPUS3 source 001b = ESIOUT1 is the PPUS3 source 010b = ESIOUT2 is the PPUS3 source 011b = ESIOUT3 is the PPUS3 source 100b = ESIOUT4 is the PPUS3 source 101b = ESIOUT5 is the PPUS3 source 110b = ESIOUT6 is the PPUS3 source 111b = ESIOUT7 is the PPUS3 source |
| 12-10 | ESIS2SELx | RW | 0h |
PPUS2 source select. These bits select the PPUS2 source for the PSM. 000b = ESIOUT0 is the PPUS2 source 001b = ESIOUT1 is the PPUS2 source 010b = ESIOUT2 is the PPUS2 source 011b = ESIOUT3 is the PPUS2 source 100b = ESIOUT4 is the PPUS2 source 101b = ESIOUT5 is the PPUS2 source 110b = ESIOUT6 is the PPUS2 source 111b = ESIOUT7 is the PPUS2 source |
| 9-7 | ESIS1SELx | RW | 0h |
PPUS1 source select. These bits select the PPUS1 source for the PSM. 000b = ESIOUT0 is the PPUS1 source 001b = ESIOUT1 is the PPUS1 source 010b = ESIOUT2 is the PPUS1 source 011b = ESIOUT3 is the PPUS1 source 100b = ESIOUT4 is the PPUS1 source 101b = ESIOUT5 is the PPUS1 source 110b = ESIOUT6 is the PPUS1 source 111b = ESIOUT7 is the PPUS1 source |
| 6-5 | ESITCH1x | RW | 0h |
These bits select the comparator input for test channel 1. 00b = Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1. 01b = Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1. 10b = Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1. 11b = Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1. |
| 4-3 | ESITCH0 | RW | 0h |
These bits select the comparator input for test channel 0. 00b = Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1. 01b = Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1. 10b = Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 . 11b = Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 . |
| 2 | ESICS | RW | 0h |
Comparator output ir Timer_A input selection 0b = The ESIEX(tsm) signal and the comparator output are connected to the TACCRx inputs. 1b = The ESIEX(tsm) signal and the ESIOUTx outputs are connected to the TACCRx inputs selected with the ESIS1SELx and ESIS2SELx bits (PPUS1 and PPUS2 signals). |
| 1 | ESITESTD | RW | 0h |
Test cycle insertion. Setting this bit inserts a test cycle between TSM cycles. ESITESTD is automatically reset at the end of the test cycle. Note that a test cycle insertion should only be done when divided ACLK is used as start trigger for TSM sequences (ESITSMTRGx = 01 and ESITSMRP=0). 0b = No test cycle inserted 1b = Test cycle inserted between TSM cycles. |
| 0 | ESIEN | RW | 0h |
Extended Scan interface enable. Setting this bit enables the Extended Scan Interface and its components. 0b = Extended Scan Interface disabled 1b = Extended Scan Interface enabled |