SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Extended Scan Interface Interrupt Register 1
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ESIIFGSET2x | ESIIFGSET1x | Reserved | ESIIE8 | ||||
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | r0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESIIE7 | ESIIE6 | ESIIE5 | ESIIE4 | ESIIE3 | ESIIE2 | ESIIE1 | ESIIE0 |
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | ESIIFGSET2x | RW | 0h |
ESIIFG8 interrupt flag source. These bits select when the ESIIFG8 flag is set. 000b = ESIIFG8 is set when ESIOUT4 is set. 001b = ESIIFG8 is set when ESIOUT4 is reset. 010b = ESIIFG8 is set when ESIOUT5 is set. 011b = ESIIFG8 is set when ESIOUT5 is reset. 100b = ESIIFG8 is set when ESIOUT6 is set. 101b = ESIIFG8 is set when ESIOUT6 is reset. 110b = ESIIFG8 is set when ESIOUT7 is set. 111b = ESIIFG8 is set when ESIOUT7 is reset. |
| 12-10 | ESIIFGSET1x | RW | 0h |
ESIIFG0 interrupt flag source. These bits select when the ESIIFG0 flag is set. 000b = ESIIFG0 is set when ESIOUT0 is set. 001b = ESIIFG0 is set when ESIOUT0 is reset. 010b = ESIIFG0 is set when ESIOUT1 is set. 011b = ESIIFG0 is set when ESIOUT1 is reset. 100b = ESIIFG0 is set when ESIOUT2 is set. 101b = ESIIFG0 is set when ESIOUT2 is reset. 110b = ESIIFG0 is set when ESIOUT3 is set. 111b = ESIIFG0 is set when ESIOUT3 is reset. |
| 9 | Reserved | R | 0h |
Reserved. This bit is always read as zero and, when written, does not affect the bit setting. |
| 8 | ESIIE8 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG8 bit. Details about the interrupt functionality can be found in the ESIIFG8 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 7 | ESIIE7 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG7 bit. Details about the interrupt functionality can be found in the ESIIFG7 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 6 | ESIIE6 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG6 bit. Details about the interrupt functionality can be found in the ESIIFG6 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 5 | ESIIE5 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG5 bit. Details about the interrupt functionality can be found in the ESIIFG5 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 4 | ESIIE4 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG4 bit. Details about the interrupt functionality can be found in the ESIIFG4 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 3 | ESIIE3 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG3 bit. Details about the interrupt functionality can be found in the ESIIFG3 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 2 | ESIIE2 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG2 bit. Details about the interrupt functionality can be found in the ESIIFG2 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 1 | ESIIE1 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG1 bit. Details about the interrupt functionality can be found in the ESIIFG1 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |
| 0 | ESIIE0 | RW | 0h |
Interrupt enable. These bits enable or disable the interrupt request for the ESIIFG0 bit. Details about the interrupt functionality can be found in the ESIIFG0 bit descriptions (see control register ESIINT2). 0b = Interrupt disabled 1b = Interrupt enabled |