SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Extended Scan Interface Processing State Machine Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ESICNT2RST | ESICNT1RST | ESICNT0RST | Reserved | ESITEST4SEL | |||
| rw-0 | rw-0 | rw-0 | r0 | r0 | r0 | rw-0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESIV2SEL | Reserved | ESICNT2EN | ESICNT1EN | ESICNT0EN | ESIQ7TRG | Reserved | ESIQ6EN |
| rw-1 | r0 | rw-0 | rw-0 | rw-0 | rw-0 | r0 | rw-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | ESICNT2RST | RW | 0h |
ESI Counter 2 reset. Setting this bit resets ESICNT2 register. After ESICNT2 register is cleared, the ESICNT2RST bit is automatically reset. This bit is always read as zero. |
| 14 | ESICNT1RST | RW | 0h |
ESI Counter 1 reset. Setting this bit resets ESICNT1 register. After ESICNT1 register is cleared, the ESICNT1RST bit is automatically reset. This bit is always read as zero. |
| 13 | ESICNT0RST | RW | 0h |
ESI Counter 0 reset. Setting this bit resets ESICNT0 register. After ESICNT0 register is cleared, the ESICNT0RST bit is automatically reset. This bit is always read as zero. |
| 12-10 | Reserved | R | 0h |
Reserved. These bits are always read as zero and, when written, do not affect the bit setting. |
| 9-8 | ESITEST4SEL | RW | 0h |
Output signal selection for ESITEST4 pin. 00b = Q2 signal from PSM table 01b = Q1 signal from PSM table 10b = TSM clock signal from Timing State Machine 11b = AFE1's comparator output signal ESIC1OUT |
| 7 | ESIV2SEL | RW | 1h |
Source Selection for V2 bit of Next State Latch 0b = PPUS3 signal is used for V2 bit 1b = Q0 is used for V2 bit |
| 6 | Reserved | R | 0h |
Reserved. This bit is always read as zero and, when written, does not affect the bit setting. |
| 5 | ESICNT2EN | RW | 0h |
ESICNT2 enable (down counter) 0b = ESICNT2 is disabled 1b = ESICNT2 is enabled |
| 4 | ESICNT1EN | RW | 0h |
ESICNT1 enable (up/down counter) 0b = ESICNT1 is disabled 1b = ESICNT1 is enabled |
| 3 | ESICNT0EN | RW | 0h |
ESICNT0 enable (up counter) 0b = ESICNT0 is disabled 1b = ESICNT0 is enabled |
| 2 | ESIQ7TRG | RW | 0h |
Enabling to use Q7 as trigger for a PSM sequence. 0b = Only ESISTOP(tsm) is used as PSM trigger. 1b = ESISTOP(tsm) and Q7 are used as PSM triggers. As soon as a PSM state is reached with Q7 bit set the next state is calculated immediately without waiting for the next falling edge of ESISTOP(tsm). |
| 1 | Reserved | R | 0h |
Reserved. This bit is always read as zero and, when written, does not affect the bit setting. |
| 0 | ESIQ6EN | RW | 0h |
Q6 enable. This bit enables Q6 for the next PSM state calculation. 0b = Q6 is not used to determine the next PSM state 1b = Q6 is used to determine the next PSM state |