Write Protection Detection flag. This flag is set when a write access is attempted while the WPROT bit is set. This bit can generate a system NMI if the WPIE bit is set (see the GCCTL0 register). This bit can be cleared by writing 0 directly or by reading the system reset vector word SYSRSTIV if it is the highest pending interrupt flag. This bit is write 0 only, write 1 has no effect.
Reset type: BOR
0h (R/W) = WPIFG_0 : No interrupt pending.
1h (R/W) = Interrupt pending. Can be cleared by writing 0 or by reading SYSSNIV when it is the highest pending interrupt.
3
ACCTEIFG
R/W
0h
Access time error flag. This flag is set when a timing violation is detected, which indicates that NWAITS[3:0] is improperly configured. When a timing violation is detected, the maximum wait state will be automatically applied to the NWAITS[3:0] to avoid further timing violation. While the ACCTEIFG bit is set, the NWAIS[3:0] cannot be overwritten and the FRAM memory write access is prohibited regardless of the WPROT bit. The ACCTEIFG bit must be cleared prior to applying a new value to NWAITS[3:0] or writing access to the FRAM memory. The timing violation (ACCTEIFG) can generate a system NMI (SYSNMI) if the Access Time Error Interrupt Enable (ACCTEIE) bit is set This bit can be cleared by writing 0 directly or by reading the system reset vector word SYSRSTIV if it is the highest pending interrupt flag. This bit is write 0 only, write 1 has no effect.
Reset type: BOR
0h (R/W) = ACCTEIFG_0 : No interrupt pending.
1h (R/W) = ACCTEIFG_1 : Interrupt pending. Can be cleared by writing 0 or by reading SYSSNIV when it is the highest pending interrupt.
2
UBDIFG
R/W
0h
FRAM uncorrectable bit error detection flag. This flag is set when an uncorrectable bit error is detected in the FRAM memory error detection logic. This bit can generate either a system NMI or a system reset (PUC). If the UBDIE bit is set, then this bit generates a system NMI, if the UBDRSTEN bit is set, then this bit generates a system reset (PUC) - see the GCCTL0 register. This bit can be cleared by writing 0 directly or by reading the system NMI vector word SYSSNIV when it is the highest pending interrupt flag. This bit is write 0 only and write 1 has no effect.
Reset type: BOR
0h (R/W) = UBDIFG_0 : No interrupt pending.
1h (R/W) = UBDIFG_1 : Interrupt pending. Can be cleared by writing 0 or by reading SYSSNIV when it is the highest pending interrupt.
1
CBDIFG
R/W
0h
FRAM correctable bit error detection flag. This flag is set when a correctable bit error is detected and corrected in the FRAM memory error detection logic. This bit can generate a system NMI if the CBDIE bit is set (see the GCCTL0 register). This bit can be cleared by software or by reading the system NMI vector word SYSSNIV if it is the highest pending interrupt flag. This bit is write 0 only and write 1 has no effect.
Reset type: BOR
0h (R/W) = CBDIFG_0 : No interrupt is pending
1h (R/W) = CBDIFG_1 : Interrupt pending. Can be cleared by writing 0 or by reading SYSSNIV if it is the highest pending interrupt.