SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
22.2.9 INTDLY (Interrupt Delay) bits
After conversion start, the position of the first output data to the internal data buffer and the first SDHSRIS.DTRDY interrupt can be adjusted by the SDHSCTL0.INTDLY delay. Any skipped data is permanently lost. The delay is applied each time conversion starts. The SDHSRIS.OVF (overflow) interrupt is not enabled for the selected number of delay samples. Figure 22-23 shows the first interrupt position when SDHSCTL0.INTDLY = 2. The window comparator feature is not applied to the skipped samples (see Section 22.2.11 for the window comparator).
Figure 22-23 First Interrupt Position With SDHSCTL0.INTDLY = 2 By the nature of sigma-delta ADC converters, if a steep and abrupt input level change (like a step function) is applied, a few samples are needed before the full input level is reached at the output. The INTDLY can be used if the unsettled output data should be skipped. This skipping is not required for most applications. See Table 22-8 for the output data settling time.
Table 22-8 Conversion Control Mode
| Input Change | SDHSCTL1.OSR Bit | Fully Settled Output Sample From the Time a Step Function is Applied | SDHSCTL0.INTDLY Value |
|---|---|---|---|
| Synchronous to fs | 10 | 5th sample | ≤4 |
| 20 | 3th sample | ≤2 | |
| 40 | 2th sample | ≤1 | |
| 80 | 1st sample | 0 | |
| 160 | 1st sample | 0 | |
| Asynchronous to fs | 10 | 6th sample | ≤5 |
| 20 | 4th sample | ≤3 | |
| 40 | 3rd sample | ≤2 | |
| 80 | 2nd sample | ≤1 | |
| 160 | 2nd sample | ≤1 |