SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The MPU can protect an address range in the main memory from unconditional external access. The size of this segment is defined by setting the upper and lower borders of this segment. To configure the segments, a lower (IBL) border and a higher (IBH) border are positioned by control register bits MPUIPSEGB1[15:0] and MPUIPSEGB2[15:0], respectively, in the MPUIPSEGBx register. The position of both borders follows the same mechanism as described in for the main segments.
The beginning of the IP encapsulation segment (IPE-segment) (IBL) is defined by the lower value of either the MPUIPSEGB1[15:0] or MPUIPSEGB2[15:0] register. The end of the IPE-segment (IBH) is defined by the higher value of either the MPUIPSEGB1[15:0] or MPUIPSEGB2[15:0] register. All memory locations addressed by the 16 most significant bits of the address bus (MAB) equal to or greater than the lower border (IBL) and less than IBH are protected.
Only program code executed from the IPE-segment can access data stored in this segment. The access rights are evaluated with each code access. Each code access outside of the IP-protected area deactivates the data access into the IPE-segment. JTAG or DMA cannot access the IPE-segment. The interrupt vector table is always open for read and write accesses (for details see Section 9.4.1).
To execute code from the IPE-segment, branch into that segment or call functions stored in that segment. Interrupt service routines can be executed from the IPE-segment, too.
Table 9-2 summarizes the possible combinations of code execution and memory access types and the resulting access rights.
An unauthorized access to the IPE-segment returns a value equivalent to the instruction "JMP $" and triggers an interrupt. In addition, the generation of a PUC can be configured.
IBL ≤ Memory Address < IBH | IBL ≤ Program Counter < IBH | JTAG or DMA Access | CPU Access |
---|---|---|---|
0FF80h ≤ Memory Address < 0FFFFh | – | Read/Write | Read/Write |
False | False | Yes | Yes |
False | True | Yes | Yes |
True | False | No | No |
True | True | No | Yes |
NOTE
IP Encapsulation area access rights do not override MPU segment rights. The IP Encapsulation rights are evaluated and if the access is granted, access rights as describe in Section 9.3 are applied.
NOTE
Code fetch from the first 8 bytes in IPE-segment does not enable data access.
The first 8 bytes within the IPE-segment do not enable data access within the IPE-segment if code is executed from that area. The start of an IPE-segment is reserved for a data structure describing the IPE-segment boundaries.
shows the segmentation of the main memory.