SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
32-Bit Hardware Multiplier Control 0 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | MPYDLY32 | MPYDLYWRTEN | |||||
| r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | rw-0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPYOP2_32 | MPYOP1_32 | MPYMx | MPYSAT | MPYFRAC | Reserved | MPYC | |
| rw | rw | rw | rw | rw-0 | rw-0 | rw-0 | rw |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | Reserved | R | 0h |
Reserved. Always reads as 0. |
| 9 | MPYDLY32 | RW | 0h |
Delayed write mode 0b = Writes are delayed until 64-bit result (RES0 to RES3) is available. 1b = Writes are delayed until 32-bit result (RES0 to RES1) is available. |
| 8 | MPYDLYWRTEN | RW | 0h |
Delayed write enable All writes to any MPY32 register are delayed until the 64-bit (MPYDLY32 = 0) or 32-bit (MPYDLY32 = 1) result is ready. 0b = Writes are not delayed. 1b = Writes are delayed. |
| 7 | MPYOP2_32 | RW | 0h |
Multiplier bit width of operand 2 0b = 16 bits 1b = 32 bits |
| 6 | MPYOP1_32 | RW | 0h |
Multiplier bit width of operand 1 0b = 16 bits 1b = 32 bits |
| 5-4 | MPYMx | RW | 0h |
Multiplier mode 00b = MPY – Multiply 01b = MPYS – Signed multiply 10b = MAC – Multiply accumulate 11b = MACS – Signed multiply accumulate |
| 3 | MPYSAT | RW | 0h |
Saturation mode 0b = Saturation mode disabled 1b = Saturation mode enabled |
| 2 | MPYFRAC | RW | 0h |
Fractional mode 0b = Fractional mode disabled 1b = Fractional mode enabled |
| 1 | Reserved | RW | 0h |
Reserved. Always reads as 0. |
| 0 | MPYC | RW | 0h |
Carry of the multiplier. It can be considered as 33rd or 65th bit of the result if fractional or saturation mode is not selected, because the MPYC bit does not change when switching to saturation or fractional mode. It is used to restore the SUMEXT content in MAC mode. 0b = No carry for result 1b = Result has a carry |