SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
4.6.3.29 RRUM
| RRUM.A | Rotate right through carry the 20-bit CPU register content | ||
| RRUM.[W] | Rotate right through carry the 16-bit CPU register content | ||
| Syntax | RRUM.A #n,Rdst | 1 ≤ n ≤ 4 | |
| RRUM.W #n,Rdst or RRUM #n,Rdst | 1 ≤ n ≤ 4 | ||
| Operation | 0 → MSB → MSB–1 ... LSB+1 → LSB → C | ||
| Description | The destination operand is shifted right by 1, 2, 3, or 4 bit positions as shown in Figure 4-53. Zero is shifted into the MSB, the LSB is shifted into the carry bit. RRUM works like an unsigned division by 2, 4, 8, or 16. The word instruction RRUM.W clears the bits Rdst.19:16. | ||
| Note : This instruction does not use the extension word. | |||
| Status Bits | N: | Set if result is negative | |
| .A: Rdst.19 = 1, reset if Rdst.19 = 0 | |||
| .W: Rdst.15 = 1, reset if Rdst.15 = 0 | |||
| Z: | Set if result is zero, reset otherwise | ||
| C: | Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) | ||
| V: | Reset | ||
| Mode Bits | OSCOFF, CPUOFF, and GIE are not affected. | ||
| Example | The unsigned address-word in R5 is divided by 16. | ||
RRUM.A #4,R5 ; R5 = R5 » 4. R5/16
| Example | The word in R6 is shifted right by 1 bit. The MSB R6.15 is loaded with 0. | ||
RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0
Figure 4-53 Rotate Right Unsigned RRUM[.W] and RRUM.A