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37.2.1.3 Sample-And-Hold
Note that the sample-and-hold circuit is only available in the analog front-end AFE1.
The sample-and-hold is used to sample the sensor voltage to be measured. Figure 37-4 shows the sample-and-hold circuitry. When ESISH = 1 and ESITEN = 0, the sample-and-hold circuitry is enabled and the excitation circuitry and mid-voltage generator are disabled. The sample-and-hold is used for resistive dividers or for other analog signals that should be sampled.
Up to four resistor dividers can be connected to ESICHx and ESICOM. AVCC and ESICOM are the common positive and negative potentials for all connected resistor dividers. When ESIEX(tsm) = 1, ESICOM is connected to ESIDVSS and allows current to flow through the dividers. This charges the capacitors of each sample-and-hold circuit to the divider voltages. All resistor divider channels are sampled simultaneously. When ESIEX(tsm) = 0, the sample-and-hold capacitor is disconnected from the resistor divider, and ESICOM is disconnected from ESIDVSS. After sampling, each channel can be measured sequentially using the channel select logic, the comparator, and the DAC.
The selected ESICHx input can be modeled as an RC low-pass filter during the sampling time, tsample, as shown in Figure 37-5. An internal MUX-on input resistance Ri(ESICHx) (3 kΩ maximum) in series with capacitor CSHC(ESICHx) (9 pF maximum) is seen by the resistor-divider. The capacitor voltage VC must be charged to within one-half LSB of the resistor divider voltage for an accurate 12-bit conversion. See the device-specific data sheet for parameters.
Figure 37-5 Analog Input Equivalent Circuit The resistance of the source RS and Ri(ESICHx) affect tsample. Equation 18 can be used to calculate the minimum sampling time tsample for a 12-bit conversion:
Substituting the values for RiESICHx and CSHC(ESICHx) given above, the equation becomes:
For example, if RS is 10 kΩ, tsamplemust be greater than 1054 ns.