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5.2.4.2 Saturation Mode
The multiplier prevents overflow and underflow of signed operations in saturation mode. The saturation mode is enabled with MPYSAT = 1 in register MPY32CTL0. If an overflow occurs, the result is set to the most-positive value available. If an underflow occurs, the result is set to the most-negative value available. This is useful to reduce mathematical artifacts in control systems on overflow and underflow conditions. The saturation mode should only be enabled when required and disabled after use.
The actual content of the result registers is not modified when MPYSAT = 1. When the result is accessed using software, the value is automatically adjusted to provide the most-positive or most-negative result when an overflow or underflow has occurred. The adjusted result is also used for successive multiply-and-accumulate operations. This allows user software to switch between reading the saturated and the nonsaturated result.
With 16×16 operations, the saturation mode only applies to the least significant 32 bits; that is, the result registers RES0 and RES1. Using the saturation mode in MAC or MACS operations that mix 16×16 operations with 32×32, 16×32, or 32×16 operations leads to unpredictable results.
With 32×32, 16×32, and 32×16 operations, the saturated result can only be calculated when RES3 is ready.
Enabling the saturation mode does not affect the content of the SUMEXT register nor the content of the MPYC bit.
; Example using
; Fractional 16x16 multiply accumulate with Saturation
; Turn on fractional and saturation mode:
BIS #MPYSAT+MPYFRAC,&MPY32CTL0
MOV &A1,&MPYS ; Load A1 for 1st term
MOV &K1,&OP2 ; Load K1 to get A1*K1
MOV &A2,&MACS ; Load A2 for 2nd term
MOV &K2,&OP2 ; Load K2 to get A2*K2
MOV &RES1,&PROD ; Save A1*K1+A2*K2 as result
BIC #MPYSAT+MPYFRAC,&MPY32CTL0 ; turn back to normal
Table 5-6 Result Availability in Saturation Mode (MPYSAT = 1)
| Operation
(OP1 × OP2) |
Result Ready in MCLK Cycles | After | ||||
|---|---|---|---|---|---|---|
| RES0 | RES1 | RES2 | RES3 | MPYC Bit | ||
| 8/16 × 8/16 | 3 | 3 | N/A | N/A | 3 | OP2 written |
| 24/32 × 8/16 | 7 | 7 | 7 | 7 | 7 | OP2 written |
| 8/16 × 24/32 | 7 | 7 | 7 | 7 | 7 | OP2L written |
| 4 | 4 | 4 | 4 | 4 | OP2H written | |
| 24/32 × 24/32 | 11 | 11 | 11 | 11 | 11 | OP2L written |
| 6 | 6 | 6 | 6 | 6 | OP2H written | |
Figure 5-4 shows the flow for 32-bit saturation used for 16×16 bit multiplications and the flow for 64-bit saturation used in all other cases. Primarily, the saturated results depends on the carry bit MPYC and the MSB of the result. Secondly, if the fractional mode is enabled, it depends also on the two MSBs of the unshift result, that is, the result that is read with fractional mode disabled.
Figure 5-4 Saturation Flow Chart NOTE
Saturation in fractional mode
In case of multiplying –1.0 × –1.0 in fractional mode, the result of +1.0 is out of range, thus, the saturated result gives the most positive result.
When using multiply-and-accumulate operations, the accumulated values are saturated as if MPYFRAC = 0; only during read accesses to the result registers the values are saturated taking the fractional mode into account. This provides additional dynamic range during the calculation and only the end result is then saturated if needed.
The following example illustrates a special case showing the saturation function in fractional mode. It also uses the 8-bit functionality of the MPY32 module.
; Turn on fractional and saturation mode,
; clear all other bits in MPY32CTL0:
MOV #MPYSAT+MPYFRAC,&MPY32CTL0
;Pre-load result registers to demonstrate overflow
MOV #0,&RES3 ;
MOV #0,&RES2 ;
MOV #07FFFh,&RES1 ;
MOV #0FA60h,&RES0 ;
MOV.B #050h,&MACS_B ; 8-bit signed MAC operation
MOV.B #012h,&OP2_B ; Start 16x16 bit operation
MOV &RES0,R6 ; R6 = 0FFFFh
MOV &RES1,R7 ; R7 = 07FFFh
The result is saturated because already the result not converted into a fractional number shows an overflow. The multiplication of the two positive numbers 00050h and 00012h gives 005A0h. 005A0h added to 07FFF FA60h results in 8000 059Fh, without MPYC being set. Because the MSB of the unmodified result RES1 is 1 and MPYC = 0, the result is saturated according Figure 5-4.
NOTE
Validity of saturated result
The saturated result is valid only if the registers RES0 to RES3, the size of OP1 and OP2, and MPYC are not modified.
If the saturation mode is used with a preloaded result, user software must ensure that MPYC in the MPY32CTL0 register is loaded with the sign bit of the written result; otherwise, the saturation mode erroneously saturates the result.