SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Table 22-11 lists the memory-mapped registers for the SDHS. All register offset addresses not listed in Table 22-11 should be considered as reserved locations and the register contents should not be modified.
Note 1: When SDHSCTL3.TRIGEN = 1,SDHSCTL0, SDHSCTL1, SDHSCTL2, SDHSCTL7, SDHSWINHITH, SDHSWINLOTH, and SDHSDTCDA registers are locked. In other words, an attempt to update those registers will be ignored.
Note 2: When SDHSCTL5.SDHS_LOCK = 1, SDHSCTL3 register is locked.
Note 3: SDHSCTL3.TRIGEN bit is a read-write bit, which is controlled by user program, wheras SDHSCTL5.SDHS_LOCK bit a read-only bit, which is a status bit that indicates whether or not the SDHS is powered-up.
Note 4: SDHSCTL3.TRIGEN bit must be set to 1 before applying a power-up signal to SDHS (SDHSON bit or an external SDHS PWR UP signal)
Note 5:
When SDHSCTL0.TRGSRC = 0:
Once SDHSCTL4.SDHSON bit is written as 1, SDHSCTL5.SDHS_LOCK bit is set immediately.
In order to update SDHS registers, clear SDHSCTL4.SDHSON bit first, and then SDHSCTL3.TRIGEN bit needs to be cleared.
When SDHSCTL0.TRGSRC = 1:
It takes up to 4 system clock cycles to set SDHSCTL5.SDHS_LOCK bit after detecting an external SDHS PWR UP signal.
In order to update SDHS registers, the SDHS_PWR_UP signal should be de-asserted first, then SDHSCTL3.TRIGEN bit needs to be cleared to be zero.
| Offset | Acronym | Register Name | Type | Reset | Section |
|---|---|---|---|---|---|
| 0h | SDHSIIDX | Interrupt Index Register | read-only | 0h | Section 22.5.1 |
| 2h | SDHSMIS | Masked Interrupt Status and Clear Register | read-only | 0h | Section 22.5.2 |
| 4h | SDHSRIS | Raw Interrupt Status Register | read-only | 0h | Section 22.5.3 |
| 6h | SDHSIMSC | Interrupt Mask Register | read-write | 0h | Section 22.5.4 |
| 8h | SDHSICR | Interrupt Clear Register. | write-only | 0h | Section 22.5.5 |
| Ah | SDHSISR | Interrupt Set Register. | write-only | 0h | Section 22.5.6 |
| Ch | SDHSDESCLO | SDHS Descriptor Register L. | read-only | 110h | Section 22.5.7 |
| Eh | SDHSDESCHI | SDHS Descriptor Register H. | read-only | BB10h | Section 22.5.8 |
| 10h | SDHSCTL0 | SDHS Control Register 0 | read-write | 8001h | Section 22.5.9 |
| 12h | SDHSCTL1 | SDHS Control Register 1 | read-write | 0h | Section 22.5.10 |
| 14h | SDHSCTL2 | SDHS Control Register 2 | read-write | 0h | Section 22.5.11 |
| 16h | SDHSCTL3 | SDHS Control Register 3 | read-write | 0h | Section 22.5.12 |
| 18h | SDHSCTL4 | SDHS Control Register 4 | read-write | 0h | Section 22.5.13 |
| 1Ah | SDHSCTL5 | SDHS Control Register 5 | read-write | 0h | Section 22.5.14 |
| 1Ch | SDHSCTL6 | SDHS Control Register 6 | read-write | 19h | Section 22.5.15 |
| 1Eh | SDHSCTL7 | SDHS Control Register 7 | read-write | Fh | Section 22.5.16 |
| 22h | SDHSDT | SDHS Data Converstion Register | read-only | 0h | Section 22.5.17 |
| 24h | SDHSWINHITH | SDHS Window Comparator High Threshold Register. | read-write | 0h | Section 22.5.18 |
| 26h | SDHSWINLOTH | SDHS Window Comparator Low Threshold Register. | read-write | 0h | Section 22.5.19 |
| 28h | SDHSDTCDA | DTC destination address register | read-write | 0h | Section 22.5.20 |