SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
JTAG Mailbox Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | |||||||
| r0 | r0 | r0 | r0 | r0 | r0 | r0 | r0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| JMBCLR1OFF | JMBCLR0OFF | Reserved | JMBM0DE | JMBOUT1FG | JMBOUT0FG | JMBIN1FG | JMBIN0FG |
| rw-(0) | rw-(0) | r0 | rw-0 | r-(1) | r-(1) | rw-(0) | rw-(0) |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | Reserved | R | 0h |
Reserved. Always reads as 0. |
| 7 | JMBCLR1OFF | RW | 0h |
Incoming JTAG Mailbox 1 flag auto-clear disable 0b = JMBIN1FG cleared on read of JMB1IN register 1b = JMBIN1FG cleared by software |
| 6 | JMBCLR0OFF | RW | 0h |
Incoming JTAG Mailbox 0 flag auto-clear disable 0b = JMBIN0FG cleared on read of JMB0IN register 1b = JMBIN0FG cleared by software |
| 5 | Reserved | R | 0h |
Reserved. Always reads as 0. |
| 4 | JMBMODE | RW | 0h |
This bit defines the operation mode of JMB for JMBI0, JMBI1, JMBO0, and JMBO1. Before switching this bit, pad and flush out any partial content to avoid data drops. 0b = 16-bit transfers using JMBO0 and JMBI0 only 1b = 32-bit transfers using JMBO0 with JMBO1 and JMBI0 with JMBI1 |
| 3 | JMBOUT1FG | R | 1h |
Outgoing JTAG Mailbox 1 flag. This bit is cleared automatically when a message is written to the upper byte of JMBO1 or as word access (by the CPU, DMA,…) and is set after the message was read through JTAG. 0b = JMBO1 is not ready to receive new data. 1b = JMBO1 is ready to receive new data. |
| 2 | JMBOUT0FG | R | 1h |
Outgoing JTAG Mailbox 0 flag. This bit is cleared automatically when a message is written to the upper byte of JMBO0 or as word access (by the CPU, DMA,…) and is set after the message was read through JTAG. 0b = JMBO0 is not ready to receive new data. 1b = JMBO0 is ready to receive new data. |
| 1 | JMBIN1FG | RW | 0h |
Incoming JTAG Mailbox 1 flag. This bit is set when a new message (provided through JTAG) is available in JMBI1. This flag is cleared automatically on read of JMBI1 when JMBCLR1OFF = 0 (auto clear mode). On JMBCLR1OFF = 1, JMBIN1FG needs to be cleared by software. 0b = JMBI1 has no new data. 1b = JMBI1 has new data available. |
| 0 | JMBIN0FG | RW | 0h |
Incoming JTAG Mailbox 0 flag. This bit is set when a new message (provided through JTAG) is available in JMBI0. This flag is cleared automatically on read of JMBI0 when JMBCLR0OFF = 0 (auto clear mode). On JMBCLR0OFF = 1, JMBIN0FG needs to be cleared by software. 0b = JMBI0 has no new data. 1b = JMBI0 has new data available. |