SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The following software example shows the recommended use of TBxIV and the handling overhead. The TBxIV value is added to the PC to automatically jump to the appropriate routine. The example assumes a single instantiation of the largest timer configuration available.
The numbers at the right margin show the necessary CPU clock cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are:
The following software example shows the recommended use of TBxIV for Timer_B3.
; Interrupt handler for TB0CCR0 CCIFG. Cycles
CCIFG_0_HND
; ... ; Start of handler Interrupt latency 6
RETI 5
; Interrupt handler for TB0IFG, TB0CCR1 through TB0CCR6 CCIFG.
TB0_HND ... ; Interrupt latency 6
ADD &TB0IV,PC ; Add offset to Jump table 3
RETI ; Vector 0: No interrupt 5
JMP CCIFG_1_HND ; Vector 2: TB0CCR1 2
JMP CCIFG_2_HND ; Vector 4: TB0CCR2 2
JMP CCIFG_3_HND ; Vector 6: TB0CCR3 2
JMP CCIFG_4_HND ; Vector 8: TB0CCR4 2
JMP CCIFG_5_HND ; Vector 10: TB0CCR5 2
JMP CCIFG_6_HND ; Vector 12: TB0CCR6 2
TB0IFG_HND ; Vector 14: TB0IFG Flag
... ; Task starts here
RETI 5
CCIFG_6_HND ; Vector 12: TB0CCR6
... ; Task starts here
RETI ; Back to main program 5
CCIFG_5_HND ; Vector 10: TB0CCR5
... ; Task starts here
RETI ; Back to main program 5
CCIFG_4_HND ; Vector 8: TB0CCR4
... ; Task starts here
RETI ; Back to main program 5
CCIFG_3_HND ; Vector 6: TB0CCR3
... ; Task starts here
RETI ; Back to main program 5
CCIFG_2_HND ; Vector 4: TB0CCR2
... ; Task starts here
RETI ; Back to main program 5
CCIFG_1_HND ; Vector 2: TB0CCR1
... ; Task starts here
RETI ; Back to main program 5