SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The output channels (CH0_OUT and CH1_OUT) have low-impedance output drivers (DRV0 and DRV1) and termination switches (SWG0 and SWG1). To support the impedance-matching requirement in application environments using ultrasonic technology, programmability is offered to the output drive strength of the drivers (DRV0 and DRV1) and the termination switches (SWG0 and SWG1). The drivers are based on inverter architecture, which consists of PMOS and NMOS. Thus, three trim registers are offered for each channel (see Table 21-1 for details).
During manufacturing, optimal impedance of the drivers and termination switches are determined and their trim values are stored to the device boot data memory (not user accessible). The output impedance of DRV0 and DRV1 are trimmed to match each other (with the lowest possible value), and the termination switches (SWG0 and SWG1) are trimmed to match the impedance of each driver. During the boot process, the trim values are written to the trim registers by bootcode. The default trim values may be different from device to device. Programmability is offered if different impedance values are preferred in a specific application environment.
| Register | Description | Trim Range (Typical)(1) |
|---|---|---|
| SAPHCH0PUT.CH0PUT | PMOS trim bits (4 bits) for the channel 0 output driver | 15 = lowest (≈ 2.5 Ω)
0 = highest Each step ≈ 3% |
| SAPHCH0PDT.CH0PDT | NMOS trim bits (4 bits) for the channel 0 output driver | 15 = lowest (≈ 2.5 Ω)
0 = highest Each step ≈ 3% |
| SAPHCH0TT | Termination switch trim bits (4 bits) for channel 0 | 15 = lowest (≈ 2.5 Ω)
0 = highest Each step ≈ 3% |
| SAPHCH1PUT.CH1PUT | PMOS trim bits (4 bits) for the channel 1 output driver | 15 = lowest (≈ 2.5 Ω)
0 = highest Each step ≈ 3% |
| SAPHCH1PDT.CH1PDT | NMOS trim bits (4 bits) for the channel 1 output driver | 15 = lowest (≈ 2.5 Ω)
0 = highest Each step ≈ 3% |
| SAPHCH1TT | Termination switch trim bits (4 bits) for channel 1 | 15 = lowest (≈ 2.5 Ω)
0 = highest Each step ≈ 3% |
The trim registers are written with the default values during every boot up; thus, if different trim values are preferred, the values must be written to the trim registers by software after every boot.
NOTE
To avoid unintended writes to the trim registers, the SAPHTACTL.UNLOCK bit can block write access to the trim registers. The trim registers are locked when SAPHTACTL.UNLOCK = 0.