SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
eUSCI_Bx Control Word Register 0
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| UCA10 | UCSLA10 | UCMM | Reserved | UCMST | UCMODEx | UCSYNC | |
| rw-0 | rw-0 | rw-0 | r0 | rw-0 | rw-0 | rw-0 | r1 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UCSSELx | UCTXACK | UCTR | UCTXNACK | UCTXSTP | UCTXSTT | UCSWRST | |
| rw-1 | rw-1 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
| Can be modified only when UCSWRST = 1. |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | UCA10 | RW | 0h |
Own addressing mode select. Modify only when UCSWRST = 1. 0b = Own address is a 7-bit address. 1b = Own address is a 10-bit address. |
| 14 | UCSLA10 | RW | 0h |
Slave addressing mode select 0b = Address slave with 7-bit address 1b = Address slave with 10-bit address |
| 13 | UCMM | RW | 0h |
Multi-master environment select. Modify only when UCSWRST = 1. 0b = Single master environment. There is no other master in the system. The address compare unit is disabled. 1b = Multi-master environment |
| 12 | Reserved | R | 0h |
Reserved |
| 11 | UCMST | RW | 0h |
Master mode select. When a master loses arbitration in a multi-master environment (UCMM = 1), the UCMST bit is automatically cleared and the module acts as slave. 0b = Slave mode 1b = Master mode |
| 10-9 | UCMODEx | RW | 0h |
eUSCI_B mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. Modify only when UCSWRST = 1. 00b = 3-pin SPI 01b = 4-pin SPI (master or slave enabled if STE = 1) 10b = 4-pin SPI (master or slave enabled if STE = 0) 11b = I2C mode |
| 8 | UCSYNC | RW | 1h |
Synchronous mode enable. For eUSCI_B always read and write as 1. |
| 7-6 | UCSSELx | RW | 3h |
eUSCI_B clock source select. These bits select the BRCLK source clock. These bits are ignored in slave mode. Modify only when UCSWRST = 1. 00b = UCLKI 01b = ACLK 10b = SMCLK 11b = SMCLK |
| 5 | UCTXACK | RW | 0h |
Transmit ACK condition in slave mode with enabled address mask register. After the UCSTTIFG has been set, the user needs to set or reset the UCTXACK flag to continue with the I2C protocol. The clock is stretched until the UCBxCTL1 register has been written. This bit is cleared automatically after the ACK has been send. 0b = Do not acknowledge the slave address 1b = Acknowledge the slave address |
| 4 | UCTR | RW | 0h |
Transmitter/receiver 0b = Receiver 1b = Transmitter |
| 3 | UCTXNACK | RW | 0h |
Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. Only for slave receiver mode. 0b = Acknowledge normally 1b = Generate NACK |
| 2 | UCTXSTP | RW | 0h |
Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode, the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. This bit is a don't care, if automatic UCASTPx is different from 01 or 10. 0b = No STOP generated 1b = Generate STOP |
| 1 | UCTXSTT | RW | 0h |
Transmit START condition in master mode. Ignored in slave mode. In master receiver mode, a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0b = Do not generate START condition 1b = Generate START condition |
| 0 | UCSWRST | RW | 1h |
0b = Disabled. eUSCI_B released for operation. 1b = Enabled. eUSCI_B logic held in reset state. |