SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
eUSCI_Bx Control Register 0
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| UCCKPH | UCCKPL | UCMSB | UC7BIT | UCMST | UCMODEx | UCSYNC | |
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UCSSELx | Reserved | UCSTEM | UCSWRST | ||||
| rw-1 | rw-1 | r0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
| Can be modified only when UCSWRST = 1. |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | UCCKPH | RW | 0h |
Clock phase select 0b = Data is changed on the first UCLK edge and captured on the following edge. 1b = Data is captured on the first UCLK edge and changed on the following edge. |
| 14 | UCCKPL | RW | 0h |
Clock polarity select 0b = The inactive state is low. 1b = The inactive state is high. |
| 13 | UCMSB | RW | 0h |
MSB first select. Controls the direction of the receive and transmit shift register. 0b = LSB first 1b = MSB first |
| 12 | UC7BIT | RW | 0h |
Character length. Selects 7-bit or 8-bit character length. 0b = 8-bit data 1b = 7-bit data |
| 11 | UCMST | RW | 0h |
Master mode select 0b = Slave mode 1b = Master mode |
| 10-9 | UCMODEx | RW | 0h |
eUSCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00b = 3-pin SPI 01b = 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 10b = 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 11b = I2C mode |
| 8 | UCSYNC | RW | 1h |
Synchronous mode enable 0b = Asynchronous mode 1b = Synchronous mode |
| 7-6 | UCSSELx | RW | 3h |
eUSCI clock source select. These bits select the BRCLK source clock. 00b = UCxCLK in slave mode. Don't use in master mode. 01b = ACLK in master mode. Don't use in slave mode. 10b = SMCLK in master mode. Don't use in slave mode. 11b = SMCLK in master mode. Don't use in slave mode. |
| 5-2 | Reserved | R | 0h |
Reserved |
| 1 | UCSTEM | RW | 0h |
STE mode select in master mode. This byte is ignored in slave or 3-wire mode. 0b = STE pin is used to prevent conflicts with other masters 1b = STE pin is used to generate the enable signal for a 4-wire slave |
| 0 | UCSWRST | RW | 1h |
Software reset enable 0b = Disabled. eUSCI reset released for operation. 1b = Enabled. eUSCI logic held in reset state. |