21.5 Ultra-Low-Power Bias Mode

The ultra-low bias power mode suppresses the PLL operation during the hold-off delay phase on USS startup. Because the PLL and its clock tree operate at a high frequency, considerable energy savings can be achieved. Common utility flow meters that enter LPM3 or LPM3.5 between the measurements with turned off USSXT benefit in particular from that mode.

Figure 21-19 shows a typical use case with register mode or auto mode. The timing axis and the amplitudes in the diagram are not to scale. Following a very short summary of that theoretical use cases... .

After an RTC event at (a), the system wakes up from LPMx, runs boot code, configures the USS trimming, and enters application code. This turns on USSXT, prepares time-out on TimerA that is running from LFXTCLK, then the CPU enters LPMx.

At (b), the TimerA service routine starts the UUPS, and the CPU enters LPMx again.

At (c), the transducers and external circuits may show ringing due to power up and bias voltage enable. The signals settle then.

At (d) the HSPLL generates a clock with almost no remaining phase variations. Near TA, the transducers have settled and the regular sequence is started by generating pulses. At TB, well before the arrival of the signal, the SDHS and its clock is enabled. At TD, the data acquisition starts.

At (e), the sequence is completed. The interrupt service routine performs calculations and sets the system to LPMx again.

Figure 21-19 Auto Mode and Register Mode Example

Figure 21-20 shows a the use case with ultra-low-power bias mode. The timing axis and the amplitudes in the diagram are not to scale. The following is a short summary of that theoretical use case:

After an RTC event at (a), the system wakes up from LPMx, runs boot code, configures the USS trimming, and enters application code. This turns on USSXT, prepares time-out on TimerA that is running from LFXTCLK, and then the CPU enters LPMx.

At (b), the TimerA service routine starts the UUPS with hold-off delay, and the CPU enters LPMx again. The UUPS state machine starts up with suppressed HSPLL.

At (c), the transducers and external circuits may show ringing due to power up and bias voltages. The signals settle then.

At (d), the HSPLL generates a clock with almost no remaining phase variations. Near TA, the transducers have settled and the regular sequence is started by generating pulses. At TB, well before the arrival of the signal, the SDHS and its clock are enabled. At TD, the data acquisition starts.

At (e), the sequence is completed. The interrupt service routine perform calculations and sets the system to LPMx again.

The ASQ.mux control signal switches between both control register sets during power up. Both register sets require same values of the corresponding control bits for a smooth bias generation and handover.

Figure 21-20 Ultra-Low-Power Bias Mode Example