Force to stop the current measurement. This bit is self cleared. No change to the power state. This bit is cleared when the stop request has been completed. Note that if this bit is set to '1' when the ASQ is idle, it is cleared immediately.

Reset type: PUC

0h (R/W) = No action

1h (R/W) = Stop the current measurement.

Force to power down the USS module. This bit is self cleared. Writing '0' has no effect. This bit is cleared when the powerdown request has been completed. Note that if this bit is set to '1' when the USS module is in OFF state, it is cleared immediately.

Reset type: PUC

0h (R/W) = No action

1h (R/W) = Stop the current measurement and power off the USS module.

Low power bias hold off delay. These bits define the duration of the hold off delay for the low power bias mode ( SAPHMCNF.LPBE=1). The hold off delay is inserted from "OFF state" to "READY state" and from "STANDBY state" to "READY state". Set these bits to zero to avoid extra delay in Register Mode and Auto Mode.

Reset type: PUC

0h (R/W) = no additional delay

1h (R/W) = additional hold off delay of ~100us (512 REFCLKs)

2h (R/W) = additional hold off delay of ~200us (1024 REFCLKs)

3h (R/W) = additional hold off delay of ~300us (1536 REFCLKs)

Enable the PSQ_START signal to the ASQ.

Note: This bit must be correcty configured before asserting the USS_PWRREQ signal.

Reset type: PUC

0h (R/W) = Do not generate the PSQ_START signal event to ASQ.

1h (R/W) = Generate the PSQ_START signal event to the ASQ.

USS Power Up trigger source select.

Reset type: PUC

0h (R/W) = CTL.USSPWRUP bit

1h (R/W) = Ext. trigger (see the device specific datasheet)

2h (R/W) = Ext. trigger (see the device-specific data sheet)

3h (R/W) = Ext. trigger (see the device-specific data sheet)

Power up the USS module. This bit is self cleared. Writing '0' has no effect.
Note: This bit is read as zero.

Reset type: PUC

0h (R/W) = No action

1h (R/W) = Power up the USS module and generate the PSQ_START to the ASQ if CTL.ASQEN = 1.
Note: This bit becomes invalid in debug mode.

Software reset

Reset type: PUC

0h (R/W) = Disabled. USS (and sub modules) reset released for operation

1h (R/W) = Enabled. USS (and sub modules) logic held in reset state

USS Busy bit. Read Only. This bit is set to '1' if one of the following conditions is met.
1) CTL.UPSTATE = 2
2) ASQ is in the middl of performing a measurement process
3) SDHS.CTL5.SDHS_LOCK = 1.

Reset type: PUC

0h (R) = The USS module is not busy.

1h (R) = The USS module is busy.

USS Power state bits. Read Only Note: Due to the synchronization issue with 2 bits, there is a very short time window that an invalid value can be read while power transition. In case an accurarte state information is needed, a simple verification would be required - Read the resister twice in a row and check if the two values are the same.

Reset type: PUC

0h (R) = USS is in OFF state

1h (R) = USS is in STANDBY state

2h (R) = USS power state is in transition.

3h (R) = USS is in READY state

USS LDO is ready.

Reset type: PUC

0h (R) = USS LDO is powered down or in transition state

1h (R) = USS LDO is powered on