SLAU646F September 2015 – June 2020
Incorrect execution of the MSP430 CPU can result from consecutive interrupt state changes (for example, EINT followed by DINT). The assembler detects such instruction patterns in code being assembled and emits warnings that NOP instructions might be required.
Since it is not always known what instruction will actually be executed after an EINT or DINT, the assembler warns if there is a NOP missing before/after every EINT or DINT, as appropriate for the device. The assembler also warns about instructions that modify the status register in a way that is unknown at assembly time, as these instructions might change the interrupt state.
Whether NOP instructions are required between interrupt state changes depends on the ISA the code is being assembled for. The assembler uses the following rules when deciding whether to warn about missing NOP instructions:
See the user guide for your device family for more details.