22.3.9 1-Wire Timing
The 1-Wire module wire control operates using the Precision Internal Oscillator (PIOSC) to provide a reliable frequency with no need for baud dividers. The register interface operates using the system clock, which may be a different clock source. However, there is no visible impact from this separate clock model. Normal rules apply to use of the registers to ensure correct operation. In particular:
- The control register is used live (not buffered) by the communication engine. Once an operation is started, it must be allowed to finish before changes are made, such as starting a new operation or changing speed. The status bits in the ONEWIRECS register notify the application if the transaction is busy or if a line-hold-low error is detected. When the last write, read or read/write has occurred, the OPC bit is set in the ONEWIRERIS register.
- Data read by the 1-Wire Master is not valid or meaningful until the 1-Wire module signals that the data is ready (through interrupt, DMA, and status).
- Data written should be written before the operation is started and then should not be re-written until the 1-Wire module signals the data has been written (through interrupt, DMA, and status).
- The 1-Wire Timing Override (ONEWIRETIM) register should not be changed while a transaction is taking place.
The ONEWIREIM, ONEWIRERIS and ONEWIREMIS registers may be written and read at any time with no risk.