12.5.1 ACMIS Register (Offset = 0x0) [reset = 0x0]
Analog Comparator Masked Interrupt Status (ACMIS)
This register provides a summary of the interrupt status (masked) of the comparators.
ACMIS is shown in Figure 12-4 and described in Table 12-6.
Return to Summary Table.
Figure 12-4 ACMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
IN2 |
IN1 |
IN0 |
| R-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
|
Table 12-6 ACMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31:3 |
RESERVED |
R |
0x0 |
|
| 2 |
IN2 |
R/W1C |
0x0 |
Comparator 2 Masked Interrupt Status.
This bit is cleared by writing a 1.
Clearing this bit also clears the IN2 bit in the ACRIS register. |
| 1 |
IN1 |
R/W1C |
0x0 |
Comparator 1 Masked Interrupt Status.
This bit is cleared by writing a 1.
Clearing this bit also clears the IN1 bit in the ACRIS register. |
| 0 |
IN0 |
R/W1C |
0x0 |
Comparator 0 Masked Interrupt Status.
This bit is cleared by writing a 1.
Clearing this bit also clears the IN0 bit in the ACRIS register. |