SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300
Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304
Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308
Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C
NOTE
This register can only be accessed from privileged mode.
The ACTIVEn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of ACTIVE1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of ACTIVE2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of ACTIVE3 corresponds to Interrupt 96; bit 17 corresponds to Interrupt 113.
See for interrupt assignments.
NOTE
Do not manually set or clear the bits in this register.
ACTIVEn is shown in Figure 2-10 and described in Table 2-20.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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