2.5.1 ACTLR Register (Offset = 0x8) [reset = 0x0]
Auxiliary Control (ACTLR)
NOTE
This register can only be accessed from privileged mode.
The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 processor and does not normally require modification.
ACTLR is shown in Figure 2-13 and described in Table 2-25.
Return to Summary Table.
Figure 2-13 ACTLR Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
DISOOFP |
DISFPCA |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DISFOLD |
DISWBUF |
DISMCYC |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 2-25 ACTLR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-10 |
RESERVED |
R |
0x0 |
|
| 9 |
DISOOFP |
R/W |
0x0 |
Disable Out-Of-Order Floating Point
Disables floating-point instructions completing out of order with respect to integer instructions.
|
| 8 |
DISFPCA |
R/W |
0x0 |
Disable CONTROL
FPCA Disable automatic update of the FPCA bit in the CONTROL register. NOTE: Two bits control when FPCA can be enabled: the ASPEN bit in the Floating-Point Context Control (FPCC) register and the DISFPCA bit in the Auxiliary Control (ACTLR) register.
|
| 7-3 |
RESERVED |
R |
0x0 |
|
| 2 |
DISFOLD |
R/W |
0x0 |
Disable IT Folding
In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding.
|
| 1 |
DISWBUF |
R/W |
0x0 |
Disable Write Buffer
|
| 0 |
DISMCYC |
R/W |
0x0 |
Disable Interrupts of Multiple Cycle Instructions
|