SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Phase Control (ADCSPC)
The ADC Sample Phase Control (ADCSPC) register is used to insert a delay in ADC module sampling. This feature can be used with the SYNCWAIT and GSYNC bit in the ADCPSSI register to provide concurrent sampling of two different signals by two different ADC modules or skewed sampling of two ADC modules to increase the effective sampling rate. For concurrent sampling, the PHASE field of each ADC module must be the same and the sample and hold times (TSHn) for the matching sample steps of each ADC must be the same. For example, both ADC0 and ADC1 would program PHASE = 0x0 in the ADCSPC register and might both have the following configuration for their ADCSSTSH0 register:
For skewed sampling with a consistent phase lag, the TSHn field in the ADCSSTSHn register must be the same for all sample steps of an ADC and for both ADC Modules. The desired lag can be calculated by adding the sample and hold time (TSHn) to the twelve clock conversion time to determine the total number of clocks in a sample period. For example to create a 180.0 degree phase lag, the PHASE of the lagging ADC is calculated as:
PHASE = (TSHn + 12)/2, where TSHn is in ADC_Clocks
For situations where a predictable phase lag is not required, sample and hold times (TSHn) of ADC modules can vary.
NOTE
Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling the AINx input may result in undesirable system consequences. The time from ADC trigger to sample is increased and could make the response time longer than anticipated. The added latency could have ramifications in the system design. Designers should carefully consider the impact of this delay.
ADCSPC is shown in Figure 10-24 and described in Table 10-17.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0x0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHASE | ||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||