SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094
These registers determine which digital comparator receives the sample from the given conversion on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set. The ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register controls the selection for Sample Sequencer 2.
ADCSSDCn is shown in Figure 10-40 and described in Table 10-34.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0x0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
S3DCSEL | S2DCSEL | S1DCSEL | S0DCSEL | ||||||||||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | ||||||||||||