10.5.21 ADCSSEMUX0 Register (Offset = 0x58) [reset = 0x0]
ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0)
This register, along with the ADCSSMUX0 register, defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. If a bit in this register is set, the corresponding MUXn field in the ADCSSMUX0 register selects from AIN[23:16]. When a bit in this register is clear, the corresponding MUXn field selects from AIN[15:0]. This register is 32 bits wide and contains information for eight possible samples.
This register is not used when the differential channel designation is used (the Dn bit is set in the ADCSSCTL0 register) because the ADCSSMUX0 register can select all the available pairs.
ADCSSEMUX0 is shown in Figure 10-35 and described in Table 10-28.
Return to Summary Table.
Figure 10-35 ADCSSEMUX0 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
EMUX7 |
RESERVED |
EMUX6 |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
EMUX5 |
RESERVED |
EMUX4 |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
EMUX3 |
RESERVED |
EMUX2 |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
EMUX1 |
RESERVED |
EMUX0 |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 10-28 ADCSSEMUX0 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-29 |
RESERVED |
R |
0x0 |
|
| 28 |
EMUX7 |
R/W |
0x0 |
8th Sample Input Select (Upper Bit).
The EMUX7 field is used during the eighth sample of a sequence executed with the sample sequencer.
0x0 = The eighth sample input is selected from AIN[15:0] using the ADCSSMUX0 register. For example, if the MUX7 field is 0x0, AIN0 is selected.
0x1 = The eighth sample input is selected from AIN[23:16] using the ADCSSMUX0 register. For example, if the MUX7 field is 0x0, AIN16 is selected.
|
| 27-25 |
RESERVED |
R |
0x0 |
|
| 24 |
EMUX6 |
R/W |
0x0 |
7th Sample Input Select (Upper Bit).
The EMUX6 field is used during the seventh sample of a sequence executed with the sample sequencer.
This bit has the same description as EMUX7.
|
| 23-21 |
RESERVED |
R |
0x0 |
|
| 20 |
EMUX5 |
R/W |
0x0 |
6th Sample Input Select (Upper Bit).
The EMUX5 field is used during the sixth sample of a sequence executed with the sample sequencer.
This bit has the same description as EMUX7. |
| 19-17 |
RESERVED |
R |
0x0 |
|
| 16 |
EMUX4 |
R/W |
0x0 |
5th Sample Input Select (Upper Bit).
The EMUX4 field is used during the fifth sample of a sequence executed with the sample sequencer.
This bit has the same description as EMUX7. |
| 15-13 |
RESERVED |
R |
0x0 |
|
| 12 |
EMUX3 |
R/W |
0x0 |
4th Sample Input Select (Upper Bit).
The EMUX3 field is used during the fourth sample of a sequence executed with the sample sequencer.
This bit has the same description as EMUX7.
|
| 11-9 |
RESERVED |
R |
0x0 |
|
| 8 |
EMUX2 |
R/W |
0x0 |
3rd Sample Input Select (Upper Bit).
The EMUX2 field is used during the third sample of a sequence executed with the sample sequencer.
This bit has the same description as EMUX7. |
| 7-5 |
RESERVED |
R |
0x0 |
|
| 4 |
EMUX1 |
R/W |
0x0 |
2th Sample Input Select (Upper Bit).
The EMUX1 field is used during the second sample of a sequence executed with the sample sequencer.
This bit has the same description as EMUX7.
|
| 3-1 |
RESERVED |
R |
0x0 |
|
| 0 |
EMUX0 |
R/W |
0x0 |
1st Sample Input Select (Upper Bit).
The EMUX0 field is used during the first sample of a sequence executed with the sample sequencer.
This bit has the same description as EMUX7. |