SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset 0x078
ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098
This register, along with the ADCSSMUX1 or ADCSSMUX2 register, defines the analog input configuration for each sample in a sequence executed with either Sample Sequencer 1 or 2. If a bit in this register is set, the corresponding MUXn field in the ADCSSMUX1 or ADCSSMUX2 register selects from AIN[23:16]. When a bit in this register is clear, the corresponding MUXn field selects from AIN[15:0]. This register is 16 bits wide and contains information for four possible samples. The ADCSSEMUX1 register controls Sample Sequencer 1 and the ADCSSEMUX2 register controls Sample Sequencer 2.
This register is not used when the differential channel designation is used (the Dn bit is set in the ADCSSCTL1 or ADCSSCTL2 register) because the ADCSSMUX1 or ADCSSMUX2 register can select all the available pairs.
ADCSSEMUXn is shown in Figure 10-41 and described in Table 10-35.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EMUX3 | RESERVED | EMUX2 | ||||
| R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EMUX1 | RESERVED | EMUX0 | ||||
| R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | ||||