SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3)
This register, along with the ADCSSMUX3 register, defines the analog input configuration for the sample in a sequence executed with Sample Sequencer 3. If EMUX0 is set, the MUX0 field in the ADCSSMUX3 register selects from AIN[23:16]. When EMUX0 is clear, the MUX0 field selects from AIN[15:0]. This register is 1 bit wide and contains information for one possible sample.
This register is not used when the differential channel designation is used (the Dn bit is set in the ADCSSCTL3 register) because the ADCSSMUX3 register can select all the available pairs.
ADCSSEMUX3 is shown in Figure 10-47 and described in Table 10-42.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EMUX0 | ||||||
R-0x0 | R/W-0x0 | ||||||