SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080
This register, along with the ADCSSEMUX1 or ADCSSEMUX2 register, defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. If the corresponding EMUXn bit in the ADCSSEMUX1 or ADCSSEMUX2 register is set, the MUXn field in this register selects from AIN[23:16]. When the corresponding EMUXn bit is clear, the MUXn field selects from AIN[15:0]. These registers are 16 bits wide and contain information for four possible samples. See the ADCSSMUX0 register on Section 10.5.15 for detailed bit descriptions. The ADCSSMUX1 register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.
NOTE
Channels AIN[31:24] do not exist on this microcontroller. Configuring MUXn to be 0x8 to 0xF when the corresponding EMUXn bit is set results in undefined behavior.
ADCSSMUXn is shown in Figure 10-37 and described in Table 10-31.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MUX3 | MUX2 | MUX1 | MUX0 | |||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||||||||||||||||||||||||