SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence 1 Sample and Hold Time (ADCSSTSH1), offset 0x07C
ADC Sample Sequence 2 Sample and Hold Time (ADCSSTSH2), offset 0x09C
These registers control the sample period size for each sample step of sequencer 1 and sequencer 2. Each sample and hold period select specifies the time allocated to the sample and hold circuit as shown by the encodings in Table 10-2.
NOTE
If sampling the internal temperature sensor, the sample and hold width should be at least 16 ADC clocks (TSHn = 0x4).
| TSHn Encoding | NSH |
|---|---|
| 0x0 | 4 |
| 0x1 | Reserved |
| 0x2 | 8 |
| 0x3 | Reserved |
| 0x4 | 16 |
| 0x5 | Reserved |
| 0x6 | 32 |
| 0x7 | Reserved |
| 0x8 | 64 |
| 0x9 | Reserved |
| 0xA | 128 |
| 0xB | Reserved |
| 0xC | 256 |
| 0xD-0xF | Reserved |
ADCSSTSHn is shown in Figure 10-42 and described in Table 10-37.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TSH3 | TSH2 | TSH1 | TSH0 | |||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||||||||||||||||||||||||