SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
AES Data R/W Plaintext/Ciphertext 0 (AES_DATA_IN_0), offset 0x060
AES Data R/W Plaintext/Ciphertext 1 (AES_DATA_IN_1), offset 0x064
AES Data R/W Plaintext/Ciphertext 2 (AES_DATA_IN_2), offset 0x068
AES Data R/W Plaintext/Ciphertext 3 (AES_DATA_IN_3), offset 0x06C
The AES Data R/W Plaintext/Ciphertext n (AES_DATA_IN_n) registers are used to read and write plaintext/ciphertext. The AES_DATA_IN_0 register contains the most significant word; the AES_DATA_IN_3 register contains least significant word.
NOTE
The AES_DATA_IN_0 register acts as a FIFO and shifts data into the other AES_DATA_IN_n registers.
AES_DATA_IN_n is shown in Figure 9-19 and described in Table 9-13.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0x0 | |||||||||||||||||||||||||||||||