9.6.3 AES_DMAMIS Register (Offset = 0x28) [reset = 0x0]
AES DMA Masked Interrupt Status (AES_DMAMIS)
The AES DMA Masked Interrupt Status (AES_DMAMIS) register displays the raw interrupts that are unmasked in the AES DMA Raw Interrupt Status (AES_DMARIS) register.
AES_DMAMIS is shown in Figure 9-29 and described in Table 9-25.
Return to Summary Table.
Figure 9-29 AES_DMAMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DOUT |
DIN |
COUT |
CIN |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 9-25 AES_DMAMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
DOUT |
R |
0x0 |
Data Out DMA Done Masked Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A DOUT interrupt has occurred.
|
| 2 |
DIN |
R |
0x0 |
Data In DMA Done Masked Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A DIN interrupt has occurred.
|
| 1 |
COUT |
R |
0x0 |
Context Out DMA Done Masked Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A COUT interrupt has occurred.
|
| 0 |
CIN |
R |
0x0 |
Context In DMA Done Raw Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A CIN interrupt has occurred.
|