9.6.2 AES_DMARIS Register (Offset = 0x24) [reset = 0x0]
AES DMA Raw Interrupt Status (AES_DMARIS)
The AES DMA Raw Interrupt Status (AES_DMARIS) register contains the raw interrupt status. If any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status bit is set to 1.
AES_DMARIS is shown in Figure 9-28 and described in Table 9-24.
Return to Summary Table.
Figure 9-28 AES_DMARIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DOUT |
DIN |
COUT |
CIN |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 9-24 AES_DMARIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
DOUT |
R/W |
0x0 |
Data Out DMA Done Raw Interrupt Status
0x0 = No Interrupt.
0x1 = The µDMA has written the last word of the process result and an interrupt has been triggered and is pending.
|
| 2 |
DIN |
R/W |
0x0 |
Data In DMA Done Raw Interrupt Status
0x0 = No Interrupt.
0x1 = The µDMA has written the last word of input data to the internal FIFO of the engine and an interrupt has been triggered and is pending.
|
| 1 |
COUT |
R/W |
0x0 |
Context Out DMA Done Raw Interrupt Status
0x0 = No Interrupt.
0x1 = The µDMA has completed the output context read from the internal register and an interrupt has been triggered and is pending.
|
| 0 |
CIN |
R/W |
0x0 |
Context In DMA Done Raw Interrupt Status
0x0 = No interrupt.
0x1 = The µDMA has completed a context write to the internal register and an interrupt has been triggered and is pending.
|