SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
AES Initialization Vector Input 0 (AES_IV_IN_0), offset 0x040
AES Initialization Vector Input 1 (AES_IV_IN_1), offset 0x044
AES Initialization Vector Input 2 (AES_IV_IN_2), offset 0x048
AES Initialization Vector Input 3 (AES_IV_IN_3), offset 0x04C
This register contains the initialization vector input.
AES_IV_IN_n is shown in Figure 9-15 and described in Table 9-9.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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