SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 1-16 shows the behavior of accesses to each region in the memory map. See Section 1.5.1 for more information on memory types and the XN attribute. MSP432E4 devices may have reserved memory areas within the address ranges listed in Table 1-16 (see Table 1-15 for more information).
| Address Range | Memory Region | Memory Type | Execute Never (XN) | Description |
|---|---|---|---|---|
| 0x0000.0000 to 0x1FFF.FFFF | Code | Normal | – | This executable region is for program code. Data can also be stored here. |
| 0x2000.0000 to 0x3FFF.FFFF | SRAM | Normal | – | This executable region is for data. Code can also be stored here. This region includes bit-band and bit-band alias areas (see Table 1-17). |
| 0x4000.0000 to 0x5FFF.FFFF | Peripheral | Device | XN | This region includes bit-band and bit-band alias areas (see Table 1-18). |
| 0x6000.0000 to 0x9FFF.FFFF | External RAM | Normal | – | This executable region is for data. |
| 0xA000.0000 to 0xDFFF.FFFF | External device | Device | XN | This region is for external device memory. |
| 0xE000.0000 to 0xE00F.FFFF | Private peripheral bus | Strongly Ordered | XN | This region includes the NVIC, system timer, and system control block. |
| 0xE010.0000 to 0xFFFF.FFFF | Reserved | – | – |
The Code, SRAM, and external RAM regions can hold programs. However, TI recommends that programs always use the Code region because the Cortex-M4F has separate buses that can perform instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more information, see Section 2.2.4.
The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from branch target addresses.