7.5.2 BOOTCFG Register (Offset = 0x1D0) [reset = 0xFFFFFFFE]

Boot Configuration (BOOTCFG)

This register is not written directly, but instead uses the FMD register as explained in Section 7.2.3.12. When this register is committed, the new value cannot be read back until after the power cycle. This register provides configuration of a GPIO pin to enable the ROM Bootloader as well as a write-once mechanism to disable external debugger access to the device. At reset, the user has the opportunity to direct the core to execute the ROM Bootloader or the application in flash memory by using a GPIO signal from Ports A through H as configured by the bits in this register (do not select PC0 to PC3, PD7, or PE7, because they are locked by default at reset). At reset, the following sequence is performed:

1. The BOOTCFG register is read. If the EN bit is clear, the ROM Bootloader is executed.
2. In the ROM Bootloader, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x00000000 and execution continues out of the ROM Bootloader.
3. If the EN bit is set or the status does not match the specified polarity, the data at address 0x00000004 is read, and if the data at this address is 0xFFFFFFFF, the ROM is mapped to address 0x00000000. and execution continues out of the ROM Bootloader.
4. If there is data at address 0x00000004 that is not 0xFFFFFFFF, the stack pointer (SP) is loaded from flash memory at address 0x00000000 and the program counter (PC) is loaded from address 0x00000004. The user application begins executing.

Figure 7-42 shows the bootloader selection sequence.

Figure 7-42 Boot Configuration Flow

The DBG0 bit is cleared by the factory and the DBG1 bit is set, which enables external debuggers. Clearing the DBG1 bit disables any external debugger access to the device, starting with the next power-up cycle of the device. The NW bit indicates that bits in the register can be changed from 1 to 0.

By committing the register values using the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained following power cycling. Before being committed, bits can only be changed from 1 to 0. All Reserved bits must remain as 1s. The reset value shown applies only to power-on reset when the register is not yet committed; any other type of reset does not affect this register. After it is committed, the register retains its value through power-on reset. When committed, the only way to restore the factory default value of this register is to perform the sequence detailed in Section 3.3.4.3.

BOOTCFG is shown in Figure 7-43 and described in Table 7-45.

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