SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The EPI Controller SDRAM interface can operate up to 60 MHz. The COUNT0 field in the EPIBAUD register configures the speed of the EPI clock. For system clock (SysClk) speeds up to 60 MHz, the COUNT0 field can be 0x0000, and the SDRAM interface can run at the same speed as SysClk. However, if SysClk is running at higher speeds, the bus interface can run only as fast as half speed, and the COUNT0 field must be configured to at least 0x0001.