SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
CAN 1 Power Domain Status (CAN1PDS)
This register provides the status of power to the CAN 1 SRAM array.
NOTE
The CAN1 memory array does not support retention and can only be turned on and off. If the memory array is currently turned on (PWRCTL = 0x3) and the power control to CAN1 is subsequently removed by clearing the P1 bit of the PCCAN register, the event causes the memory array to turn off and the MEMSTAT bit in the CAN1PDS register to be 0x0 (array off).
CAN1PDS is shown in Figure 4-46 and described in Table 4-53.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | MEMSTAT | PWRSTAT | ||||
R-0x0 | R-0x3 | R-0x3 | R-0x3 | ||||