SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
After a tamper event, the HIB Tamper Log (HIBTPLOGn) registers and the NMI to the processor may be cleared by writing a 1 to the TPCLR bit in the HIBTPCTL register. This clear status is reflected by the STATE bit in the HIBSTPSTAT register changing from 0x2 back to a 0x1. If the source of the tamper event comes from an XOSC failure, the clearing of a tamper event is delayed while the clock is switched to LFIOSC. The NMI interrupt handler may access the module immediately, but should read the HIBTPLOGn registers before issuing a tamper clear in the HIBTPCTL register.
NOTE
The HIBTPLOG7 register is sticky and is only cleared by a Hibernate module reset.