SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four JTAG/SWD pins and the NMI pin. For pin numbers, see . Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see Section 17.5.10), GPIO Pull Up Select (GPIOPUR) register (see Section 17.5.15), GPIO Pull-Down Select (GPIOPDR) register (see Section 17.5.16), and GPIO Digital Enable (GPIODEN) register (see Section 17.5.18) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see Section 17.5.19) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see Section 17.5.20) have been set.