19.4.2 Configure the I2C Master to High Speed Mode
To configure the I2C master to high-speed mode:
- Enable the I2C clock using the RCGCI2C register in the System Control module (see Section 4.2.93).
- Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System Control module (see Section 4.2.87). To find out which GPIO port to enable, see the device-specific data sheet.
- In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register (see Section 17.5.10). To determine which GPIOs to configure, see the device-specific data sheet.
- Enable the I2CSDA pin for open-drain operation. See Section 17.5.14.
- Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate pins. SeeSection 17.5.22 and the device-specific data sheet.
- Initialize the I2C master by writing the I2CMCR register with a value of 0x0000.0010.
- Set the desired SCL clock speed of 3.33 Mbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by Equation 64:
TPR = (System Clock / (2 × (SCL_LP + SCL_HP) × SCL_CLK)) – 1
TPR = (80 MHz / (2 × (2 + 1) × 3330000)) – 1
Equation 64. TPR = 3
Write the I2CMTPR register with the value of 0x0000.0003.
- To send the master code byte, software should place the value of the master code byte into the I2CMSA register and write the I2CMCS register with the following value depending on the required operation:
- For standard high-speed mode, write 0x13 to the I2CMCS register.
- For burst high-speed mode, write 0x50 to the I2CMCS register.
- This places the I2C master peripheral in high-speed mode, and all subsequent transfers (until STOP) are carried out at high-speed data rate using the normal I2CMCS command bits, without setting the HS bit in the I2CMCS register.
- The transaction is ended by setting the STOP bit in the I2CMCS register.
- Wait until the transmission completes by polling the BUSBSY bit in the I2CMCS register until it has been cleared.
- Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.