SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The LCD controller is configured to support 16-bpp raw data format when TFT24 = 0x0, LCDTFT = 0x1, TFTMAP = 0x0 in the LCDRASTRCTL register. Two 16-bpp raw data pixels can be stored in one word in DDR (see Figure 20-8). For color component ordering, pixel data is in a RGB565 configuration and is output on the LCD pixel data bus LCDDATA [15:0] in the same order. LCDDATA bits [23:16] are undefined in 16-bpp mode. Figure 20-9 shows the configuration of the pixel data retrieved from memory and LCD bus output.