SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP)
The DCGCACMP register lets software enable and disable the analog comparator module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
NOTE
This register controls the clocking for the analog comparator module.
DCGCACMP is shown in Figure 4-146 and described in Table 4-153.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0x0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | D0 | ||||||||||||||
R-0x0 | R/W-0x0 | ||||||||||||||