| 31-18 |
RESERVED |
R |
0x0 |
|
| 17 |
D17 |
R/W |
0x0 |
GPIO Port T Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port T is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port T in deep-sleep mode.
|
| 16 |
D16 |
R/W |
0x0 |
GPIO Port S Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port S is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port S in deep-sleep mode.
|
| 15 |
D15 |
R/W |
0x0 |
GPIO Port R Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port R is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port R in deep-sleep mode.
|
| 14 |
D14 |
R/W |
0x0 |
GPIO Port Q Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port Q is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port Q in deep-sleep mode.
|
| 13 |
D13 |
R/W |
0x0 |
GPIO Port P Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port P is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port P in deep-sleep mode.
|
| 12 |
D12 |
R/W |
0x0 |
GPIO Port N Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port N is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port N in deep-sleep mode.
|
| 11 |
D11 |
R/W |
0x0 |
GPIO Port M Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port M is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port M in deep-sleep mode.
|
| 10 |
D10 |
R/W |
0x0 |
GPIO Port L Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port L is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port L in deep-sleep mode.
|
| 9 |
D9 |
R/W |
0x0 |
GPIO Port K Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port K is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port K in deep-sleep mode.
|
| 8 |
D8 |
R/W |
0x0 |
GPIO Port J Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port J is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port J in deep-sleep mode.
|
| 7 |
D7 |
R/W |
0x0 |
GPIO Port H Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port H is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port H in deep-sleep mode.
|
| 6 |
D6 |
R/W |
0x0 |
GPIO Port G Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port G is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port G in deep-sleep mode.
|
| 5 |
D5 |
R/W |
0x0 |
GPIO Port F Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port F is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port F in deep-sleep mode.
|
| 4 |
D4 |
R/W |
0x0 |
GPIO Port E Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port E is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port E in deep-sleep mode.
|
| 3 |
D3 |
R/W |
0x0 |
GPIO Port D Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port D is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port D in deep-sleep mode.
|
| 2 |
D2 |
R/W |
0x0 |
GPIO Port C Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port C is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port C in deep-sleep mode.
|
| 1 |
D1 |
R/W |
0x0 |
GPIO Port B Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port B is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port B in deep-sleep mode.
|
| 0 |
D0 |
R/W |
0x0 |
GPIO Port A Deep-Sleep Mode Clock Gating Control
0x0 = GPIO port A is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to GPIO port A in deep-sleep mode.
|